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?2002 fairchild semiconductor corporation fqd18n20v2 / fqu18n20v2 qfet tm rev. b1, august 2002 fqd18n20v2 / fqu18n20v2 200v n-channel mosfet general description these n-channel enhancement mode power field effect transistors are produced using fairchild?s proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for low voltage applications such as automotive, high efficiency switching for dc/dc converters, and dc motor control. features ? 15a, 200v, r ds(on) = 0.14 ? @v gs = 10 v ? low gate charge ( typical 20 nc) ? low crss ( typical 25 pf) ? fast switching ? 100% avalanche tested ? improved dv/dt capability absolute maximum ratings t c = 25c unless otherwise noted thermal characteristics symbol parameter fqd18n20v2 / fqu18n20v2 units v dss drain-source voltage 200 v i d drain current - continuous (t c = 25c) 15 a - continuous (t c = 100c) 9.75 a i dm drain current - pulsed (note 1) 60 a v gss gate-source voltage 30 v e as single pulsed avalanche energy (note 2) 340 mj i ar avalanche current (note 1) 15 a e ar repetitive avalanche energy (note 1) 8.3 mj dv/dt peak diode recovery dv/dt (note 3) 6.5 v/ns p d power dissipation (t a = 25c) * 2.5 w power dissipation (t c = 25c) 83 w - derate above 25c 0.67 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering purposes, 1/8 " from case for 5 seconds 300 c symbol parameter typ max units r jc thermal resistance, junction-to-case -- 1.5 c / w r ja thermal resistance, junction-to-ambient * -- 50 c / w r ja thermal resistance, junction-to-ambient -- 110 c / w * when mounted on the minimum pad size recommended (pcb mount) ! " ! ! ! " " " ! " ! ! ! " " " s d g i-pak fqu series d-pak fqd series gs d gs d
rev. b1, august 2002 fqd18n20v2 / fqu18n20v2 ?2002 fairchild semiconductor corporation electrical characteristics t c = 25c unless otherwise noted notes: 1. repetitive rating : pulse width limited by maximum junction temperature 2. l = 1.58mh, i as = 18a, v dd = 50v, r g = 25 ?, starting t j = 25c 3. i sd 18a, di/dt 200a/ s, v dd bv dss, starting t j = 25c 4. pulse test : pulse width 300 s, duty cycle 2% 5. essentially independent of operating temperature symbol parameter test conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 200 -- -- v ? bv dss / ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c -- 0.25 -- v/c i dss zero gate voltage drain current v ds = 200 v, v gs = 0 v -- -- 1 a v ds = 160 v, t c = 125c -- -- 10 a i gssf gate-body leakage current, forward v gs = 30 v, v ds = 0 v -- -- 100 na i gssr gate-body leakage current, reverse v gs = -30 v, v ds = 0 v -- -- -100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 3.0 -- 5.0 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 7.5 a -- 0.12 0.14 ? g fs forward transconductance v ds = 40 v, i d = 7.5 a (note 4) -- 11 -- s dynamic characteristics c iss input capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz -- 830 1080 pf c oss output capacitance -- 200 260 pf c rss reverse transfer capacitance -- 25 33 pf c oss output capacitance v ds = 160 v, v gs = 0 v, f = 1.0 mhz -- 70 -- pf c oss eff. effective output capacitance v ds = 0v to 160 v, v gs = 0 v -- 135 -- pf switching characteristics t d(on) turn-on delay time v dd = 100 v, i d = 18 a, r g = 25 ? (note 4, 5) -- 16 40 ns t r turn-on rise time -- 133 275 ns t d(off) turn-off delay time -- 38 85 ns t f turn-off fall time -- 62 135 ns q g total gate charge v ds = 160 v, i d = 18 a, v gs = 10 v (note 4, 5) -- 20 26 nc q gs gate-source charge -- 5.6 -- nc q gd gate-drain charge -- 10 -- nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -- -- 15 a i sm maximum pulsed drain-source diode forward current -- -- 60 a v sd drain-source diode forward voltage v gs = 0 v, i s = 15 a -- -- 1.5 v t rr reverse recovery time v gs = 0 v, i s = 18 a, di f / dt = 100 a/ s (note 4) -- 158 -- ns q rr reverse recovery charge -- 1.0 -- c
?2002 fairchild semiconductor corporation fqd18n20v2 / fqu18n20v2 rev. b1, august 2002 typical characteristics 0 5 10 15 20 25 0 2 4 6 8 10 12 v ds = 100v v ds = 40v v ds = 160v note : i d = 18a v gs , gate-source voltage [v] q g , total gate charge [nc] 10 -1 10 0 10 1 0 500 1000 1500 2000 2500 c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd notes : 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitance [pf] v ds , drain-source voltage [v] 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 10 -1 10 0 10 1 25 150 notes : 1. v gs = 0v 2. 250 s pulse test i dr , reverse drain current [a] v sd , source-drain voltage [v] 0 102030405060 0.0 0.1 0.2 0.3 0.4 0.5 v gs = 20v v gs = 10v note : t j = 25 r ds(on) [ ], drain-source on-resistance i d , drain current [a] 10 -1 10 0 10 1 10 -1 10 0 10 1 v gs top : 15.0 v 10.0 v 8.0 v 7.0 v 6.5 v 6.0 v bottom : 5.5 v notes : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] v ds , drain-source voltage [v] figure 5. capacitance characteristics figure 6. gate charge characteristics figure 3. on-resistance variation vs. drain current and gate voltage figure 4. body diode forward voltage variation vs. source current and temperature figure 2. transfer characteristics figure 1. on-region characteristics 45678910 10 -1 10 0 10 1 notes : 1. v ds = 40v 2. 250 s pulse test -55 150 25 i d , drain current [a] v gs , gate-source voltage [v]
?2002 fairchild semiconductor corporation fqd18n20v2 / fqu18n20v2 rev. b1, august 2002 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -2 10 -1 10 0 notes : 1 . z jc (t) = 1.5 /w m a x . 2 . d u ty f a c to r, d = t 1 /t 2 3 . t jm - t c = p dm * z jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 z jc (t), therm al r esponse t 1 , square w ave pulse duration [sec] 25 50 75 100 125 150 0 5 10 15 20 i d , drain current [a] t c , case temperature [ ] 10 0 10 1 10 2 10 -1 10 0 10 1 10 2 dc 10 ms 1 ms 100 us operation in this area is limited by r ds(on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] v ds , drain-source voltage [v] typical characteristics (continued) figure 11. transient thermal response curve t 1 p dm t 2 -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 notes : 1. v gs = 10 v 2. i d = 7.5 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = 250 a bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] figure 9. maximum safe operating area figure 7. breakdown voltage variation vs. temperature figure 8. on-resistance variation vs. temperature figure 10. maximum drain current vs. case temperature
?2002 fairchild semiconductor corporation fqd18n20v2 / fqu18n20v2 rev. b1, august 2002 charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs e as =li as 2 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l i d t p e as =li as 2 ---- 2 1 e as =li as 2 ---- 2 1 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l l i d i d t p gate charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms
?2002 fairchild semiconductor corporation fqd18n20v2 / fqu18n20v2 rev. b1, august 2002 peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
?2002 fairchild semiconductor corporation fqd18n20v2 / fqu18n20v2 dimensions in millimeters rev. b1, august 2002 package dimensions 6.60 0.20 2.30 0.10 0.50 0.10 5.34 0.30 0.70 0.20 0.60 0.20 0.80 0.20 9.50 0.30 6.10 0.20 2.70 0.20 9.50 0.30 6.10 0.20 2.70 0.20 min0.55 0.76 0.10 0.50 0.10 1.02 0.20 2.30 0.20 6.60 0.20 0.76 0.10 (5.34) (1.50) (2xr0.25) (5.04) 0.89 0.10 (0.10) (3.05) (1.00) (0.90) (0.70) 0.91 0.10 2.30typ [2.30 0.20] 2.30typ [2.30 0.20] max0.96 (4.34) (0.50) (0.50) dpak
?2002 fairchild semiconductor corporation fqd18n20v2 / fqu18n20v2 dimensions in millimeters rev. b1, august 2002 package dimensions (continued) 6.60 0.20 0.76 0.10 max0.96 2.30typ [2.30 0.20] 2.30typ [2.30 0.20] 0.60 0.20 0.80 0.10 1.80 0.20 9.30 0.30 16.10 0.30 6.10 0.20 0.70 0.20 5.34 0.20 0.50 0.10 0.50 0.10 2.30 0.20 (0.50) (0.50) (4.34) ipak
?2002 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i1 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. fact? fact quiet series? fast ? fastr? frfet? globaloptoisolator? gto? hisec? i 2 c? implieddisconnect? isoplanar? littlefet? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? pacman? pop? power247? powertrench ? qfet? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? slient switcher ? smart start? spm? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet ? vcx? acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? across the board. around the world? the power franchise? programmable active droop?
careers | sitema go datasheets, samples, buy technical information applications design center support company investors my f a home >> find products >> product status/pricing/packaging fqd18n20v2 200v n-channel advanced qfet v2 series general description back to top features back to top contents ? general description ? features ? product status/pricing/packaging ? order samples ? models ? qualification support these n-channel enhancement mode pow er field effect transistors are produced using fairchild?s proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switchin g performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for low voltage applications such as automotive, high efficiency switching for dc/dc converters, and dc motor control. z 15a, 200v, r ds(on) = 0.14 ? @v gs = 10 v z low gate charge ( typical 20 nc) z low crss ( typical 25 pf) z fast switching z 100% avalanche tested z improved dv/dt capability datasheet download this datasheet e - mail this datasheet this page print version product product status pb-free status pricing* package type leads packing method package marking convention** line 1: $y (fairchild logo) related links request samples how to order products product change notices (pcns) support sales support quality and reliability design cente r pa g e 1 of 2 product folder - fairchild p/ n fqd18n20v2 - 200v n-channe l advanced qfet v2 series 17-au g -2007 mhtml:file://c:\temp\fqd18n20v2tf.mht
back to top models back to top qualification support click on a product for detailed qualification data back to top fqd18n20v2tf full production $1.08 to - 252(dpak) 2 tape reel & z (asm. plant code) &e& 3 (3-digit date code) line 2: dv2 line 3: 18n20 FQD18N20V2TM full production $1.08 to - 252(dpak) 2 tape reel line 1: $y (fairchild logo) & z (asm. plant code) &e& 3 (3-digit date code) line 2: dv2 line 3: 18n20 * fairchild 1,000 piece budgetary pricing ** a sample button will appear if the part is available through fa irchild's on-line samples program. if there is no sample butt on, please contact a fairchild distributo r to obtain samples indicates product with pb -free second-level interconne ct. for more information click here. package marking information for product fqd18n20v2 is available. click here for more information . package & leads condition temperature range vcc range software version revision date pspice to-252(dpak)-2 electrical/thermal -55c to 150c 0v to 50v orcad 10.3 jun 27, 2007 product fqd18n20v2tf FQD18N20V2TM ? 2007 fairchild semiconductor products | design center | support | company news | investors | my fairchild | contact us | site index | privacy policy | site terms & conditions | standard terms & conditions o pa g e 2 of 2 product folder - fairchild p/ n fqd18n20v2 - 200v n-channe l advanced qfet v2 series 17-au g -2007 mhtml:file://c:\temp\fqd18n20v2tf.mht

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